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publication# 15434 rev. h amendment /0 issue date: february 1996 2-184 palce20ra10 family 24-pin asynchronous ee cmos programmable array logic final com'l: h-7/10/15/20 ind: h-7/10/15/20 distinctive characteristics n low power at 100 ma i cc n as fast as 7.5 ns maximum propagation delay and 100 mhz f max (external) n individually programmable asynchronous clock, preset, reset, and enable n registered or combinatorial outputs n programmable polarity n programmable replacement for high-speed cmos or ttl logic n ttl-level register preload for testability n extensive third-party software and programmer support through fusionpld partners n 24-pin pdip and 28-pin plcc packages save space n 7.5 ns, 10 ns, and 15 ns versions utilize split leadframes for improved performance general description the palce20ra10 is an advanced pal device built with low-power, high-speed, electrically-erasable cmos technology. the palce20ra10 offers asyn- chronous clocking for each of the ten flip-flops in the de- vice. the ten macrocells feature programmable clock, preset, reset, and enable, and all can operate asynchronously to other macrocells in the same device. the palce20ra10 also has flip-flop bypass, allowing any combination of registered and combinatorial outputs. the palce20ra10 utilizes the familiar sum-of-prod- ucts (and/or) architecture that allows users to imple- ment complex logic functions easily and efficiently. multiple levels of combinatorial logic can always be re- duced to sum-of-products form, taking advantage of the very wide input gates available in pal devices. the equations are programmed into the device through floating-gate cells in the and logic array that can be erased electrically. block diagram output enable
2-185 palce20ra10 family connection diagrams top view v cc pl 15434h-2 i 0 i 1 i 2 i 3 i 4 i 5 i 6 i 7 i 8 i 9 gnd i/o 9 i/o 8 i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 1 i/o 0 oe 15434h-3 note: pin 1 is marked for orientation. 1 3 5 7 9 11 12 10 2 4 8 6 24 22 20 18 14 13 15 23 21 17 19 16 skinnydip plcc jedec 1 234 28 27 26 255 24 23 22 21 20 19 1817 1615 6 7 8 9 10 11 12 13 14 i 2 i 3 i 4 nc i 5 i 6 i 7 i/o 7 i/o 6 i/o 5 nc i/o 4 i/o 3 i/o 2 i/o 1 i/o 0 oe nc i 8 i 9 gnd nc pl i 0 i 1 vcc i/o 9 i/o 8 pin designations gnd = ground i = input i/o = input/output nc = no connect oe = output enable pl = preload v cc = supply voltage
2-186 palce20ra10h-7/10/15/20 (com'l, ind) ordering information commercial and industrial products package type p = 24-pin 300 mil plastic skinnydip (pd3024) j = 28-pin plastic leaded chip carrier (pl 028) i p r o g r a m m a b l e l o g i c p r o d u c t s f o r c o m m e r c i a l a n d i n d u s t r i a l a p p l i c a t i o n s a r e a v a i l a b l e w i t h s e v e r a l o r d e r i n g o p t i o n s . t h e order number (valid combination) is formed by a combination of: valid combinations pal 20 ra 10 -7 j family type pal = programmable array logic number of array inputs output type ra = registered asynchronous number of outputs power h = half power (i cc = 100 ma) operating conditions c = commercial (0 c to +75 c) i = industrial (C40 c to +85 c) technology ce = cmos electrically erasable speed -7 = 7.5 ns t pd -10 = 10 ns t pd -15 = 15 ns t pd -20 = 20 ns t pd ce h palce20ra10h-7 palce20ra10h-10 palce20ra10h-15 palce20ra10h-20 valid combinations valid combinations lists configurations planned to be supported in volume for this device. consult y o u r l o c a l s a l e s o f f i c e t o c o n f i r m a v a i l a b i l i t y o f specific valid combinations and to check on newly released combinations. pc, jc, pi, ji jc, ji
2-187 palce20ra10 family commercial and industrial products 15434h-5 d q pl p 1 0 pl oe output ap ar s 0 figure 1. palce20ra10 macrocell functional description the palce20ra10 has ten dedicated input lines and ten programmable i/o macrocells. the registered asynchronous (ra) macrocell is shown in figure 1. pl serves as global register preload and oe serves as global output enable. programmable output polarity is available to provide user-programmable output polarity for each individual macrocell. the programmable functions in the palce20ra10 are automatically configured from the users design specifi- cation, which can be in a number of formats. the design specification is processed by development software to verify the design and create a programming file. this file, once downloaded to a programmer, configures the device according to the users desired function. programmable preset and reset in each macrocell, two product lines are dedicated to asynchronous preset and asynchronous reset. if the preset product line is high, the q output of the register becomes a logic 1 and the output pin will be a logic 0. if the reset product line is high, the q output of the regis- ter becomes a logic 0 and the output pin will be logic 1. the operation of the programmable preset and reset overrides the clock. combinatorial/registered outputs if both the preset and reset product lines are high, the flip-flop is bypassed and the output becomes combina- torial. otherwise, the output is from the register. each output can be configured to be combinatorial or registered. programmable clock the clock input to each flip-flop comes from the pro- grammable array, allowing any flip-flop to be clocked independently if desired. ar ap dq ar combinatorial/active low registered/active low registered/active high ap dq combinatorial/active high 15434h-6 figure 2. macrocell configurations
2-188 palce20ra10 family three-state outputs the devices provide a product term dedicated to local output control. there is also a global output control pin. the output is enabled if both the global output control pin is low and the local output control product term is high. if the global output control pin is high, all outputs will be disabled. if the local output control product term is low, then that output will be disabled. security bit a security bit is also provided to prevent unauthorized copying of pal device patterns. once the bit is pro- grammed, the circuitry enabling verification is perma- nently disabled, and the array will read as if every bit is programmed. with verification not operating, it is impos- sible to simply copy the pal device pattern on a pal de- vice programmer. the security bit can only be erased in conjunction with the entire pattern. programmable polarity the outputs can be programmed either active-low or active-high. this is represented by the exclusive-or gate shown in the palce20ra10 logic diagram. when the output polarity bit is programmed, the lower input to the exclusive-or gate is high, so the output is active- high. similarly when the output polarity bit is unprogrammed, the output is active-low. the pro- grammable output polarity feature allows the user a higher degree of flexibility when writing equations. programming and erasing the palce20ra10 can be programmed on standard logic programmers. approved programmers are listed at the end of this databook. it also may be erased to re- set a previously configured device back to its virgin state. erasure is automatically performed by the pro- gramming hardware. no special erase operation is re- quired. output register preload the output registers on the palce20ra10 can be preloaded from the output pins to facilitate functional testing of complex state machine designs. this feature allows direct loading of arbitrary states, making it unnec- essary to cycle through long test vector sequences to reach a desired state. in addition, transitions from illegal states can be verified by loading illegal states and ob- serving proper recovery. register preload is controlled by a ttl-level signal, making it a convenient board-level initialization function. details on output register preload can be found on page 16. power-up reset all flip-flops power up to a logic low for predictable system initialization. registered outputs of the palce20ra10 will be high due to the output inverter. the state of combinatorial outputs will be a function of the logic. details on power-up reset can be found on page 16. quality and testability the palce20ra10 offers a very high level of built-in quality. the erasability of the device provides a means of verifying performance of all ac and dc parameters. in addition, this verifies complete programmability and functionality of the device to provide the highest pro- gramming yields and post-programming functional yields in the industry. technology the high-speed palce20ra10 is fabricated with o u r a d v a n c e d e l e c t r i c a l l y e r a s a b l e ( e e ) c m o s p r o c - ess. the array connections are formed with proven ee cells. inputs and outputs are designed to be compatible with ttl devices. this technology provides strong input clamp diodes, output slew-rate control, and a grounded substrate for clean switching.
2-189 palce20ra10 family logic diagram skinnydip (plcc jedec) pinouts 36 37 38 39 36 37 38 39 0 1 2 3 4 5 6 7 8 9 1011 12131415 16171819 20212223 24252627 28293031 32333435 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 8 9 1011 12131415 16171819 20212223 24252627 28293031 32333435 1 0 dq ap ar pl p 1 0 dq ap ar pl p 1 0 dq ap ar pl p 1 0 dq ap ar pl p 1 0 dq ap ar pl p 1 0 dq ap ar pl p 1 0 dq ap ar pl p 1 0 dq ap ar pl p 1 0 dq ap ar pl p 1 0 dq ap ar pl p 1 (2) 2 (3) 3 (4) 4 (5) 5 (6) 6 (7) 7 (9) 8 (10) 9 (11) 11 (13) 10 (12) 12 (14) 23 (27) 24 (28) v cc 22 (26) 21 (25) 20 (24) 19 (23) 18 (21) 17 (20) 16 (19) 15 (18) 14 (17) 13 (16) 15434h-7
2-190 palce20ra10h-7/10/15/20 (com'l, ind) absolute maximum ratings storage temperature C65 c to +150 c . . . . . . . . . . . ambient temperature with power applied C55 c to +125 c . . . . . . . . . . . . . supply voltage with respect to ground C0.5 v to +7.0 v . . . . . . . . . . . . . dc input voltage C0.5 v to v cc + 0.5 v . . . . . . . . . . . dc output or i/o pin voltage C0.5 v to v cc + 0.5 v . . . . . . . . . . . . . . . static discharge voltage 2001 v . . . . . . . . . . . . . . . . . latchup current (t a = C40 c to +85 c) 100 ma . . . . . . . . . . . . . . . . . . stresses above those listed under absolute maximum rat- ings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maxi- mum ratings for extended periods may affect device reliabil- ity. programming conditions may differ. operating ranges commercial (c) devices ambient temperature (t a ) operating in free air 0 c to +75 c . . . . . . . . . . . . . . supply voltage (v cc ) with respect to ground +4.75 v to +5.25 v . . . . . . . . industrial (i) devices ambient temperature (t a ) operating in free air C40 c to +85 c . . . . . . . . . . . . supply voltage (v cc ) with respect to ground +4.5 v to +5.5 v . . . . . . . . . . . . . . operating ranges define those limits between which the func- tionality of the device is guaranteed. dc characteristics over commercial and industrial operating ranges unless otherwise specified parameter symbol parameter description test conditions min max unit v oh output high voltage i oh = C3.2 ma 2.4 v v in = v ih or v il v cc = min v ol output low voltage i ol = 16 ma 0.4 v v in = v ih or v il v cc = min v ih input high voltage guaranteed input logical high 2.0 v voltage for all inputs (note 1) v il input low voltage guaranteed input logical low 0.8 v voltage for all inputs (note 1) i ih input high leakage current v in = 5.5 v, v cc = max 10 m a i il input low leakage current v in = 0 v, v cc = max C100 m a i ozh off-state output leakage v out = 5.5 v, v cc = max 10 m a current high v in = v il or v ih (note 2) i ozl off-state output leakage v out = 0 v, v cc = max C100 m a current low v in = v il or v ih (note 2) i sc output short-circuit current v out = 0.5 v, v cc = max (note 3) C30 C130 ma i cc commercial supply current v in = 0 v, outputs open -7/10/15 100 ma (static) i out = 0 ma, v cc = max, (note 4) -20 90 ma i cc industrial supply current v in = 0 v, outputs open -7/10/15 115 ma (static) i out = 0 ma, v cc = max, (note 4) -20 100 ma notes: 1. these are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. i/o pin leakage is the worst case of i il and i ozl (or i ih and i ozh ). 3. not more than one output should be tested at a time. duration of the short-circuit should not exceed one second. v out = 0.5 v has been chosen to avoid test problems caused by tester ground degradation. 4. this parameter is guaranteed under worst case test conditions.
2-191 palce20ra10h-7/10/15/20 (com'l, ind) capacitance (note 1) parameter symbol parameter description test conditions typ unit c in input capacitance inputs v in = 2.0 v v cc = 5.0 v 5 oe t a = +25 c9 c out output capacitance v out = 2.0 v f = 1 mhz 8 pf note: 1. these parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. switching characteristics over commercial and industrial operating ranges (note 2) parameter min min min min symbol parameter description (3) max (3) max (3) max (3) max unit t pd input or feedback to combinatorial output 7.5 10 15 20 ns t s setup time from input, feedback or sp to clock 2.5 3 4 4 ns t h hold time 2.5 3 4 4 ns t co clock to output or feedback 7.5 10 15 20 ns t ap asynchronous preset to registered output 7.5 10 15 20 ns t apw asynchronous preset width (note 3) 5 8 10 12 ns t apr asynchronous preset recovery time (note 3) 5 7 10 12 ns t ar asynchronous reset to registered output 7.5 10 15 20 ns t arw asynchronous reset width (note 3) 5 8 10 12 ns t arr asynchronous reset recovery time (note 3) 5 7 10 12 ns t wl low 4 5 8 12 n s t wh high 4 5 8 12 n s external feedback 1/(t s + t co ) 100 76.9 52.6 37 mhz no feedback 1/(t wh + t wl ) 125 100 62.5 41.6 mhz t pzx oe to output enable 5 8 10 15 ns t pxz oe to output disable 5 8 10 15 ns t ea input to output enable using product 7.5 10 15 20 ns term control t er input to output disable using product 7.5 10 15 20 ns term control t wp preload pulse duration 5 7 10 15 ns t sp preload setup time 5 7 10 15 ns t hp preload hold time 5 7 10 15 ns -7 -10 -15 -20 clock width maximum frequency (note 4) f max notes: 2. see switching test circuit for test conditions. 3. these parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where these parameters may be affected. 4. these parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where the frequency may be affected.
2-192 palce20ra10 family switching waveforms t apr t pd input or feedback combinatorial output v t v t 15434h-8 combinatorial output v t v t input or feedback output input to output disable/enable 15434h-13 t er t ea v t input or feedback registered output registered output 15434h-9 t s t co v t t h v t clock v t t wh clock clock width t wl 15434g-12 v t v t oe output oe to output disable/enable 15434h-14 t pzx t pxz v oh - 0.5v v ol + 0.5v v oh - 0.5v v ol + 0.5v notes: 1. v t = 1.5 v 2. input pulse amplitude 0 v to 3.0 v 3. input rise and fall times 2 ns C 5 ns typical. registered output t apw t ap v t v t asynchronous preset input asserting asynchronous preset 15434h-10 clock v t v t t arr t arw v t t ar asynchronous reset 15434h-11 clock registered output input asserting asynchronous reset v t
2-193 palce20ra10 family key to switching waveforms ks000010-pal must be steady may change from h to l may change from l to h does not apply dont care, any change permitted will be steady will be changing from h to l will be changing from l to h changing, state unknown center line is high- impedance off state waveform inputs outputs switching test circuit 15434h-15 c l output r 1 r 2 s 1 test point 5 v measured specification s 1 c l r 1 r 2 output value t pd , t co closed all except h-20: all except h-20: 1.5 v t pzx , t ea z ? h: open 50 pf 300 w 300 w 1.5 v z ? l: closed t pxz , t er h ? z: open 5 pf h-20: 560 w h-20: 1.1 k w h ? z: v oh C 0.5 v l ? z: closed l ? z: v ol + 0.5 v commercial and industrial
2-194 palce20ra10 family typical i cc characteristics v cc = 5 v, t a = 25 c 60 50 40 30 20 10 0 0 1 5 101520 frequency (mhz) i cc (ma) 15434h-16 the selected typical pattern utilized 50% of the device resources. half of the macrocells were programmed as registered, and the other half were programmed as combinatorial. half of the available product terms were used for each macrocell. on any vector, half of the outputs were switching. by utilizing 50% of the device, a midpoint is defined for i cc . from this midpoint, a designer may scale the i cc graphs up or down to estimate the i cc requirements for a particular design. i cc vs. frequency 150 80 70 25 30 35 40 50 palce20ra10 family
2-195 palce20ra10 family endurance characteristics t h e p a l c e 2 0 r a 1 0 i s m a n u f a c t u r e d u s i n g our ad- vanced electrically erasable process. this technology uses an ee cell to replace the fuse link used in bipolar parts. as a result, the device can be erased and reprogrammeda feature which allows 100% testing at the factory. symbol parameter test conditions min unit t dr min pattern data retention time max storage temperature 10 years max operating temperature 20 years n min reprogramming cycles normal programming conditions 100 cycles robustness the palce20ra10 has been designed with some unique features that make it extremely robust, even when operating in high-speed design environments. pull-up resistors on the inputs and i/os cause uncon- nected pins to default to the high state. please note that these pull-up resistors are only for this purpose, and do not provide enough current to sufficiently pull a bus l i n e h i g h . we recommend that external pull-up or pull-down resistors be used if the condition of a floating bus line exists. input-clamping circuitry limits negative overshoot, elimi- nating the possibility of false clocking caused by subse- quent ringing. a special noise filter makes the programming circuitry completely insensitive to any positive overshoot that has a pulse width of less than about 100 ns. input/output equivalent schematics 15434h-17 typical input typical output preload circuitry esd protection and clamping feedback input v cc v cc > 50 k w v cc programming voltage detection positive overshoot filter programming circuitry provides esd protection and clamping programming pins only > 50 k w v cc
2-196 palce20ra10 family power-up reset the palce20ra10 has been designed with the capa- bility to reset during system power-up. following power- up, all flip-flops will be reset to low. the output state will be high independent of the logic polarity. this fea- ture provides extra flexibility to the designer and is espe- cially valuable in simplifying state machine initialization. a timing diagram and parameter table are shown below. due to the synchronous operation of the power-up reset and the wide range of ways v cc can rise to its steady state, two conditions are required to ensure a valid power-up reset. these conditions are: the v cc rise must be monotonic. following reset, the clock input must not be driven from low to high until all applicable input and feedback setup times are met. parameter symbol parameter descriptions max unit t pr power-up reset time 1000 ns t s input or feedback setup time t wl clock width low see switching characteristics 15434h-18 t pr t wl t s 4 v v cc power registered output clock power-up reset waveform output register preload the preload function allows the register to be loaded from the output pins. this feature aids functional testing of sequential designs by allowing direct setting of output states. the procedure for preloading follows. 1. disable output registers. 2. apply either v ih or v il to all registered outputs. leave combinatorial outputs floating. 3. pulse pl from v ih to v il to v ih . 4. remove v il /v ih from all registered output pins. 5. enable the output registers. 6. verify v ol /v oh at all registered output pins. note that because of the output inverter, a register that has been preloaded high will provide a low at the output. also note that because there is an in- verter on the register preload input, the level pre- sented on the register preload input at the time of preload will be present on the register output pin following the preload sequence e.g., a low on the register pin at the time of preload will result in a low on that pin after preload. 15434h-19 t wl t ea output disable/enable register outputs pin 1 preload clock t hp t s t er output register preload waveform

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